The present invention relates to a semiconductor device and, more particularly, a semiconductor device provided with a bi-polar transistor of npn type.
FIG. 1A is a plane view showing a typical conventional bi-polar transistor of npn type employed in the semiconductor integrated circuit device and FIG. 1B is a sectional view taken along a line B--B in FIG. 1A.
Reference numeral 1 represents a p-type silicon substrate. An epitaxial silicon layer of n.sup.- -type is formed on the p-type silicon substrate 1. An isolation diffusion layer 2 is formed in the epitaxial silicon layer, in contact with the p-type silicon substrate 1. An n.sup.- -type collector region 3 of npn bi-polar transistor is isolated by this isolation diffusion layer 2. An n.sup.+ -type buried layer 4 is formed between the n.sup.- -type collector region 3 and the p-type silicon substrate 1. On the other hand, an n.sup.+ -type region 7 for forming a collector electrode and a p.sup.+ -type base region 5 are formed adjacent to the upper portion of n.sup.- -type collector region 3. An n.sup.+ -type emitter region 6 is formed adjacent to the upper portion of p.sup.+ -type base region 5.
The upper surface of the epitaxial layer is covered by an insulating film (not shown). On the insulation film are formed emitter, base and collector electrodes which are ohmic-contacted through a contact hole with the n.sup.+ -type emitter region 6, p.sup.+ -type base region 5 or n.sup.+ -type region 7.
It is well-known that with a bi-polar transistor having a construction as described above, the storage of minority carriers (or holes in the case) occurs at the n.sup.- -type collector region 3 when the transistor is operated in the saturation range (which typically happens when the collector electrode is opened and base current is flowed from the p.sup.+ -type base region 5 to the n.sup.+ -type emitter region 6). As a result, this minority carrier storage acts as a trigger, causing a parasitic transistor of pnp type, which comprises the p.sup.+ -type base region 5, n.sup.- -type collector region 3, p-type substrate 1 and p.sup.+ -type isolation diffusion layer 2, to be operated, said p.sup.+ -type base region 5 functioning as an emitter, n.sup.- -type collector rgion 3 as a base, and p-type substrate 1 and p.sup.+ -type isolation layer 2 as a collector. The occurrence of this parasitic pnp transistor lowers the reliability of the device depending upon its location in the intergrated circuit.
Therefore, a construction shown in FIGS. 2A and 2B has been employed to suppress the influence of a pnp type parasitic transistor caused in a typical npn type bi-polar transistor. FIG. 2A is a plane view similar to FIG. 1A and showing this improved npn type bi-polar transistor, and FIG. 2B is a sectional view taken along a line B--B in FIG. 2A. The same portions as those in FIGS. 1A and 1B are represented by the same reference numerals.
In the case of this improved npn transistor, an n.sup.+ -type guard ring 7' is formed in the upper portion of n.sup.- -type collector region 3, enclosing the p.sup.+ -type base region 5. Guard ring 7' also functions as the n.sup.+ -type region 7 for forming the collector electrode as in FIGS. 1A and 1B. Thanks to this n.sup.+ -type guard ring 7', h.sub.FE (forward current gain) of the common emitter configuration parasitic pnp transistor is lowered and less current is allowed to flow to the p-type substrate 1 as compared with the npn transistor shown in FIGS. 1A and 1B.
In the case where the improved npn transistor shown in FIGS. 2A and 2B and the npn transistor shown in FIGS. 1A and 1B are manufactured on a same standard, the distance between the n.sup.+ -type guard ring 7' and the p.sup.+ -type isolation diffusion layer 2 in the improved npn transistor must be made same as between the p.sup.+ -type base region 5 and the p.sup.+ -type isolation diffusion layer 2 in the transistor shown in FIGS. 1A and 1B. In the case of the improved npn transistor shown in FIGS. 2A and 2B, therefore, the width of n.sup.- -type collector region 3, that is, the base width of the parasitic pnp transistor is substantially enlarged. Since h.sub.FE of the bi-polar transistor becomes smaller as its base width becomes larger, h.sub.FE of the parasitic pnp transistor is further lowered because the width of n-type collector region 3 is substantially enlarged in the improved npn transistor.
Even in the case of the improved npn transistor, however, the operation of the parasitic pnp transistor causes relatively large current to flow to the p-type substrate 1 and the problem of reliability caused by this current is still left unsolved.